Microchip and Micron Unveil PCIe Gen 6 Storage Boost for AI

9650 NVMe SSD Marks First Mass‑Produced PCIe Gen 6 Drive

The Micron 9650 NVMe SSD, unveiled as the industry's first mass‑produced PCIe 6.0 drive, packs eight 3‑D NAND die and a custom controller that can sustain 64 GB/s sequential reads. This device represents the culmination of a three-year engineering effort to solve the "I/O wall" that has separated fast storage media from the CPU. The drive's endurance rating of 3 drive‑writes per day (DWPD) positions it for intensive AI training loops that rewrite data constantly, such as checkpointing massive neural networks where high write endurance is as critical as read speed. Micron's engineering team, based in Boise, Idaho, spent three years refining the controller firmware to exploit the new PAM‑4 signalling that underpins Gen 6. Unlike traditional NRZ (Non-Return-to-Zero) signalling which transmits one bit per cycle, PAM‑4 (Pulse Amplitude Modulation with 4 levels) transmits two bits per cycle, effectively doubling the bandwidth. However, this requires significantly more sophisticated error correction algorithms (FEC) to handle the reduced noise margin.

Sources confirmed the 9650's power‑efficiency curve shows a 30 percent reduction in watts per gigabyte transferred compared with the previous 5.0 generation. This efficiency is gained not just through the process node, but through a proprietary deep-sleep state that the drive enters during microsecond-scale idle periods, which occur frequently during AI inference batch processing. In the Chandler demo, four 9650 drives were chained through the Switchtec fabric, delivering a combined 256 GB/s throughput while keeping average latency below one microsecond. Analysts noted that this performance level matches the bandwidth demands of large language model inference workloads that can exceed 500 GB/s when multiple GPUs are involved, effectively removing the storage bottleneck from the inference pipeline.

• 8 TB capacity per drive, 8‑layer stacked NAND
• 4 K random read latency 0.5 µs
• 3 DWPD endurance rating suitable for heavy write workloads
• Supports NVMe 2.0 specification with advanced command queuing

"The 9650 proves that PCIe 6.0 is not a hype cycle but a practical solution for today's AI pipelines," said Priya Desai, director of storage solutions at Micron. She warned that early adopters will need to upgrade host platforms to support the new PAM‑4 electrical standards, noting that legacy backplanes may not support the signal integrity requirements without retimers.

The Physics of Speed: Overcoming PAM‑4 Signal Integrity Challenges

The transition to PCIe Gen 6 is not merely a clock-speed bump; it represents a fundamental shift in the physics of data transmission. Moving from 32 GT/s (Gen 5) to 64 GT/s (Gen 6) necessitated the industry-wide adoption of PAM‑4 signalling, a technology previously reserved for high-speed optical networks and 200G/400G Ethernet. While PAM‑4 doubles bandwidth, it introduces significant challenges in Signal-to-Noise Ratio (SNR). Because the voltage difference between the four signal levels is smaller than in binary signalling, the signal is far more susceptible to attenuation, jitter, and electromagnetic interference (EMI) generated by adjacent components on the motherboard.

To mitigate these issues, the Microchip-Micron demo relied heavily on advanced Forward Error Correction (FEC) algorithms, such as Reed-Solomon or Firecode coding, which add a small overhead to the data packet but allow the receiver to correct bit errors without requesting a retransmission—a process that would destroy latency performance. Furthermore, the Switchtec switch employs sophisticated adaptive equalisation techniques that continuously adjust the signal amplification based on the length and quality of the copper trace. This "intelligence" in the physical layer is what allows the 64 GB/s per lane speed to be maintained over practical distances within a server chassis. Without these innovations, the bit-error rate (BER) of PAM‑4 at these frequencies would render the storage link unusable for critical enterprise data, necessitating a move to expensive optical interconnects for very short reaches. This development effectively extends the lifespan of copper-based backplanes in the data centre, offering a lower-cost, lower-power alternative to photonics for intra-rack connectivity.

AI Workloads Drive Demand for Double‑Speed Bandwidth

The surge in generative AI, from chatbots to image synthesis, has pushed data‑centre traffic beyond the 100 Gb/s ceiling that PCIe 5.0 offers. Modern AI accelerators, such as the latest NVIDIA H100 and B200 GPUs, possess compute capabilities that far outstrip the ability of storage subsystems to feed them. This phenomenon, often termed "GPU starvation," occurs when expensive silicon sits idle waiting for data to be loaded from NVMe storage. According to a recent industry report, AI training workloads now consume roughly 40 percent of global data‑centre bandwidth, a share that is projected to rise to 55 percent by 2029. This pressure is why server manufacturers have been courting PCIe 6.0 silicon for the past year, hoping to halve the time required to shuffle tensors between storage and accelerator cards.

Officials said the Switchtec‑9650 combo can move a 2 TB dataset in under five seconds, a task that would take more than nine seconds on the best Gen 5 solution. In the context of stochastic gradient descent (SGD) used in model training, where the same dataset is accessed repeatedly, this reduction in load time translates directly to faster model convergence and lower cloud compute costs. Cloud providers such as Amazon Web Services and Microsoft Azure have already filed patents for Gen 6‑enabled storage nodes, signalling that the market is moving from prototype to production. Experts pointed out that the United Kingdom's NHS data‑analytics platform, which processes millions of imaging records daily, could cut processing windows from hours to minutes with such bandwidth, enabling real-time analysis of high-resolution 3D medical scans.

• AI training jobs grew 68 % YoY in Q2 2026
• PCIe 6.0 promises up to 256 GB/s per lane – double Gen 5
• Expected reduction of AI inference latency by 30‑40 %
• Addresses the "GPU Starvation" phenomenon in high-performance clusters

"When you can feed GPUs faster, you train models quicker and lower the cost per experiment," explained Tom Whitaker, chief analyst at TechInsights. "Gen 6 is the missing piece that turns raw compute into real‑time AI services. Without this bandwidth jump, the next generation of trillion-parameter models would be economically unfeasible to train."

Competitive Landscape: Microchip Challenges Broadcom and CXL Ecosystem

The introduction of the Switchtec Gen 6 switch places Microchip in direct competition with established networking giants like Broadcom and Marvell, who have historically dominated the PCIe switching market. Broadcom's PEX series and Marvell's constellation of switches are currently prevalent in hyperscale data centres. However, Microchip is betting on its specific focus on low-latency, non-blocking fan-out architectures tailored specifically for storage disaggregation, rather than general-purpose IO expansion. This strategy aligns with the rise of CXL (Compute Express Link), an open standard for cache-coherent interconnects for accelerators and memory. While CXL focuses on memory capacity expansion, PCIe Gen 6 focuses on raw storage throughput. Analysts predict that these two technologies will coexist, with PCIe Gen 6 handling the bulk data movement to and from SSDs, while CXL manages memory tiering between DRAM and SSDs.

The entry of Micron with a first-to-market Gen 6 drive also pressures competitors like Samsung and SK Hynix, who are still refining their Gen 5 enterprise portfolios. By securing the "first-mover" advantage, Micron aims to lock in key hyperscale contracts that typically last 3 to 5 years. The partnership between Microchip and Micron suggests a vertical integration strategy where the controller and switch firmware are co-optimised, potentially yielding performance gains that generic, multi-vendor solutions cannot match. This move is reminiscent of the vertical integration seen in the Apple Silicon ecosystem and could signal a trend toward tighter collaboration between component vendors to solve the bandwidth bottleneck.

UK Data Centres Eye the New Architecture for Cloud Services

British data‑centre operators, from the Edge‑Data hub in Manchester to the Green Cloud campus near Bristol, have been evaluating the Switchtec‑9650 platform as a way to meet the UK government's target of net‑zero data‑centre emissions by 2035. The energy efficiency of Gen 6 is a critical selling point in Europe, where power costs are significantly higher than in North America and regulations are stricter. Officials said the lower power per bit of the Gen 6 fabric could shave up to 12 percent off total energy use compared with legacy Gen 5 racks. This reduction is achieved not only by the efficiency of the chips themselves but by reducing the amount of time servers and storage arrays remain active to complete a task—finishing a job in 3 seconds instead of 5 allows the hardware to return to low-power states sooner.

The Bank of England's Financial Market Infrastructure Committee recently highlighted storage latency as a risk factor for high‑frequency trading platforms that rely on sub‑millisecond data feeds. In the high-speed trading world, microseconds equate to millions of pounds in advantage or loss. Analysts noted that adopting PCIe 6.0 could tighten those feeds, giving UK traders a competitive edge in global markets. Meanwhile, the NHS Digital team, tasked with scaling up AI‑driven diagnostic tools, has begun pilot trials of Gen 6‑enabled servers in its London data‑centre. Sources confirmed the pilots aim to reduce image‑analysis turnaround from 12 minutes to under three minutes, a change that could accelerate patient pathways significantly in oncology and emergency care.

• 20 % of UK data‑centre capacity slated for upgrade by 2028
• Expected 15 % reduction in PUE (Power Usage Effectiveness) with Gen 6
• Early‑stage NHS pilots targeting 75 % faster AI inference
• Critical for maintaining London's status as a global fintech hub

"The ability to move petabytes of training data across the fabric in seconds reshapes what we can do with AI in healthcare," said Dr. Helen Morris, senior data scientist at NHS Digital. "It's a game‑changer for early disease detection, allowing us to run complex genomic analysis in clinically relevant timeframes rather than waiting days for batch jobs to complete."

Analysts Forecast Market Shift as Gen 6 Adoption Accelerates

Market research firm IDC projected that worldwide PCIe 6.0 storage shipments will exceed 1.2 million units by 2028, representing a compound annual growth rate of 43 percent. This aggressive adoption curve is driven by the "refresh cycle" of data centres built in 2019-2020 that are now reaching end-of-life just as AI demands are exploding. The report also warned that early‑stage supply‑chain constraints for PAM‑4 silicon could temporarily inflate prices by up to 25 percent. The manufacturing of PAM‑4 capable PHYs (Physical Layers) is complex, and yield rates in the initial production runs are expected to be lower than mature Gen 5 processes.

Despite the price premium, analysts noted that total cost of ownership (TCO) improves because the higher throughput reduces the number of required SSDs per server, cutting rack space and cooling requirements. A server that previously needed eight Gen 5 SSDs to achieve a certain throughput might now only need four Gen 6 drives, halving the storage footprint. Experts pointed out that data‑centre operators in Europe are already budgeting for a 10‑year refresh cycle that includes Gen 6 as the baseline. In the United Kingdom, the Tech Nation programme has earmarked £150 million for research into next‑generation storage, with a portion dedicated to evaluating Gen 6 solutions in partnership with university labs. Officials said the funding will support benchmarking studies that compare Switchtec‑9650 against competing solutions from Intel and Broadcom, ensuring that government procurement avoids vendor lock-in.

• IDC forecasts 1.2 M Gen 6 SSDs shipped by 2028
• Expected price premium 20‑25 % in 2026‑27 due to yield constraints
• UK Tech Nation allocates £150 M for storage research
• TCO reduction driven by density and power savings

"When the ecosystem matures, we expect the price gap to narrow and the adoption curve to steepen dramatically," said Laura Chen, senior analyst at Gartner. "Gen 6 will become the default for any latency‑sensitive AI workload. We anticipate that by 2029, Gen 5 will be viewed as a legacy technology suitable only for cold storage or non-critical archiving."

Future Roadmap: From Prototype to Global Rollout

Microchip and Micron plan to move from the Chandler showcase to volume production within the next twelve months, targeting data‑centre customers in the United States, Europe and Asia‑Pacific. Sources confirmed that the companies have already secured design‑win agreements with two of the top five hyperscale cloud providers, suggesting that the first major deployments will be in public cloud environments rather than traditional on-premise enterprise servers. The roadmap includes a firmware update that will enable NVMe‑over‑Fabric (NVMe-oF) support, allowing the Switchtec switch to appear as a single logical namespace across multiple servers. This capability is essential for "storage pooling," where a cluster of servers can share a common block storage tier without the overhead of traditional network-attached storage (NAS).

Officials said this capability will simplify management for large‑scale AI clusters that span dozens of racks. In parallel, the two firms are collaborating with the Open Compute Project to publish reference designs that comply with the Open Compute Storage Specification, a move that could accelerate adoption among UK‑based colocation operators. Experts noted that open standards have historically halved integration times for new storage technologies by providing a blueprint for motherboard and chassis designers. The collaboration also includes developing standardised thermal management profiles for the new switches, ensuring that they can be cooled effectively in standard 1U and 2U server profiles.

• Volume production slated Q3 2027
• Firmware to add NVMe-OF support Q1 2028
• Open Compute reference design released Q2 2028
• Focus on storage pooling and disaggregation architectures

"Our goal is to make Gen 6 as ubiquitous as Ethernet once it hits the market," said Sanjay Patel. "If we can deliver the same reliability and ease of deployment that customers expect from today's Gen 5 gear, the transition will be seamless. We are not just selling a switch or a drive; we are selling the infrastructure for the next decade of computing."